/*-----------------------------------------------------------------------------
v0_filter
Created (24.10.2013)
Created by Alina Ivanova
Version 2.0
v0 filter for example
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
-- SystemVerilog v0_filter
-------------------------------------------------------------------------------*/
module v0_filter
#(
	parameter SIZE_ADC_DATA                                  = 11;
	parameter SIZE_FILTER_DATA                               = 15;
	parameter DELAY                                          = 10)
(
	input  wire                                              reset,
	input  wire                                              clk,
//------------------------------------------------------------------------
	input  wire [SIZE_ADC_DATA:0]                            input_data,
//------------------------------------------------------------------------
	output reg [SIZE_ADC_DATA:0]                             output_data);

	reg                                                      a;
	reg                                                      b;
	reg        [1:0]                                         c;
	reg        [SIZE_ADC_DATA:0]                             signal_delay [DELAY:0];
	wire                                                     f;

	assign f                                                 = input_data[1];

	always @ (posedge clk or negedge reset)
	begin
		if (!reset)
		begin
			a                                              <= 0;
			b                                              <= 0;
			c                                              <= 0;
			for (integer i = 0; i<=DELAY; i++)
			begin
				signal_delay[i]                            <= 0;
			end
			output_data                                    <= 0;
		end
		else
		begin
			signal_delay[0]                                <= input_data;
			for (integer i = 1; i<=DELAY; i++)
			begin
				signal_delay[i]                            <= signal_delay[i-1];
			end
			output_data                                    <= signal_delay[3];
			a                                              <= ~b;
			c                                              <= a + b;
		end
	end
endmodule

